Traditional circuit static analysis works on netlists generated by logic synthesis. This circuit analysis attempts to identify structure patterns by traversing the netlists generated by logic synthesis. A netlist describes the connectivity of an electronic design. Netlists usually convey connectivity information and can provide instances, nets, and perhaps some attributes. Netlists have an abstraction layer that is structural, because netlists describe connectivity of an electronic design. The major ingredients of the netlists are logic elements, such as the flip-flops and the combinatorial gates, and their connectivity.
Current circuit structure analysis tools work on netlists synthesized from codes in hardware description language. The structure pattern matching procedures are implemented manually. One has to develop matching algorithms for each structure pattern. This approach is not flexible. Given the design variants and the differences in synthesizers, it is easy to miss or falsely recognize some structure patterns.